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CXA3503R driver/timing generator for color lcd panels description the CXA3503R is an ic designed to drive the color lcd panels lcx032 and lcx033. this ic greatly reduces the number of peripheral circuits and parts by incorporating a rgb driver and timing generator for video signals onto a single chip. this chip has a built-in serial interface circuit and electronic attenuators which allow various settings to be performed by microcomputer control, etc. features color lcd panel lcx032 and lcx033 driver supports ntsc and pal systems supports 16:9 wide display (letter box and pulse elimination display) supports y/color difference and rgb inputs supports osd input (digital input) power saving function serial interface circuit electronic attenuators (d/a converter) trap and lpf (f0, fc variable) common output circuits sharpness function 2-point correction circuit r, g, b signal delay time adjustment circuit d/a output pin (0 to 3v, 8 level output) output polarity inversion circuit supports ac drive for lcd panel during no signal applications color lcd viewfinders absolute maximum ratings (ta = 25?) supply voltage v cc 16 v v cc 215 v v cc 315 v v dd 5.5 v analog input pin voltage vina (pins 57, 58 and 59) gnd ?0.3 to v cc 1 + 0.3 v vina (pins 3, 69) v cc 1v vina (pin 30) 1.5 to v cc 2 ?4 v vina (pin 71) 0.9 vp-p vina (pins 70, 72) 0.8 vp-p digital input pin voltage vind (other than pins 5, 10, 14, 15 and 16) v ss ?0.3 to v dd + 0.3 v vind (pins 5, 10) v ss ?0.3 to +5.5 v common input pin voltage vinad (pins 14, 15 and 16) gnd, v ss ?0.3 to +5.5 v operating temperature topr ?5 to +75 ? storage temperature tstg ?5 to +150 ? allowable power dissipation p d (ta 25?) 737 mw operating conditions supply voltage v cc 1 ?gnd1 2.7 to 3.6 v v cc 2 ?gnd2 11.0 to 14.0 v v cc 3 ?gnd3 11.0 to 14.0 v v dd ?vss 2.7 to 3.6 v input voltage sig.c voltage vsig.c 5.0 to 6.5 v rgb input signal voltage (pins 70, 71 and 72) ? 1 vrgb 0 to 0.7 (0.5 typ.) vp-p y input signal voltage (pin 71) ? 2 vy 0 to 0.5 (0.35 typ.) vp-p r-y input voltage (pin 72) ? 2 vr-y 0 to 0.49 (0.245 typ.) vp-p b-y input voltage (pin 70) ? 2 vb-y 0 to 0.622 (0.311 typ.) vp-p ? 1 during rgb input ? 2 during y/color difference input ?1 e99733b1x sony reserves the right to change products and specifications without prior notice. this information does not convey any licens e by any implication or otherwise under any patents or other right. application circuits shown, if any, are typical examples illustr ating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits. 72 pin lqfp (plastic)
?2 CXA3503R block diagram 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 vss fil out sync in sync out csync/hd da out tst1 f adj gnd1 vd vst tst2 tst3 sck sen sdat r inject v ss g out g dc det r out r dc det b out b dc det sig.c gnd2 gnd2 tst4 hdo vdo xclr rpd vss cki cko v dd v dd +3.0v +3.0v +3.0v +3.0v vss vss gnd1 vss mck v dd tst15 osd b osd r osd g blk hck1 hck2 vcc1 hst rgt en stb vck fil in b/b-y g/y da r/r-y vss vss tst14 tst13 tst12 tst11 tst10 tst9 dwn pof tst8 gnd3 com vcc3 tst7 tst6 tst5 vcc2 clk clp +12.0v +12.0v gnd3 vss vss s/p conv register dac phase comparator pll counter hsync det h skew det v control v position pulse elm h.filter sync sep mode hdo gen vdo gen s/h s/h gen hck gen osd rgb trap lpf clamp filter bias hcounter hpulse gen pol sw gamma clamp blk-lim user-bright g r b sub-bright ck control buf u-brt mode lpf filter pic-g hue color pic-f cont sub-brt r sub-brt b 1 2 whitlim sub-cont r sub-cont b blklim com-dc buf buf buf buf sig.c contrast g r b clamp matrix dl1 dl1 picture hue v counter v sep
3 CXA3503R pin description pin no. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 v ss fil out sync in sync out csync/hd da out tst1 f adj gnd1 vd vst tst2 tst3 sck sen sdat r inject v ss v dd v dd cko cki v ss rpd xclr vdo hdo tst4 gnd2 sig.c b dc det b out r dc det r out g dc det g out v cc 2 o i o i o o i o i i i o o i o i o o i o o o o o o digital 3.0v gnd h filter output (for using internal sync separation) sync separation circuit input (for using internal sync separation) sync separation circuit output (for using internal sync separation) csync/horizontal sync signal input dac output test (leave this pin open.) trap f0 adjusting resistor connection analog 3.0v gnd vertical sync signal input v start pulse output test (leave this pin open.) test (leave this pin open.) serial clock input serial load input serial data input serial block current controlling resistor connection digital 3.0v gnd digital 3.0v power supply digital 3.0v power supply oscillation cell output oscillation cell input digital 3.0v gnd phase comparator output power-on reset capacitor connection (timing generator block) vdo pulse output hdo pulse output test (connect to gnd.) analog 12.0v gnd r, g and b output dc voltage adjustment b signal dc voltage feedback circuit capacitor connection b signal output r signal dc voltage feedback circuit capacitor connection r signal output g signal dc voltage feedback circuit capacitor connection g signal output analog 12.0v power supply l h symbol i/o description input pin for open status
4 CXA3503R pin no. 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 tst5 tst6 tst7 v cc 3 com gnd3 tst8 pof dwn tst9 tst10 tst11 tst12 tst13 tst14 v ss v ss v dd tst15 osd b osd r osd g blk hck1 hck2 v cc 1 hst rgt en stb vck fil in b/b-y g/y r/r-y o o o i i i o o o o o o o o i i i i test (leave this pin open.) test (leave this pin open.) test (leave this pin open.) analog 12.0v com power supply common pad voltage for lcd panel output analog 12.0v com gnd test (leave this pin open.) lcd panel power supply on/off (leave this pin open when not using this function.) right/left inversion switching signal output test (connect to gnd.) test (connect to gnd.) test (leave this pin open.) test (leave this pin open.) test (leave this pin open.) test (leave this pin open.) digital 3.0v gnd digital 3.0v gnd digital 3.0v power supply test (connect to gnd.) osd b input osd r input osd g input blk pulse output h clock pulse 1 output h clock pulse 2 output analog 3.0v power supply h start pulse output right/left inversion switching signal output en pulse output stb pulse output v clock pulse output h filter input (for using internal sync separation) b/b-y signal input g/y signal input r/r-y signal input symbol i/o description input pin for open status ? dwn: down scan and up scan, rgt: right scan and left scan h: pull-up processing, l: pull-down processing
5 CXA3503R analog block pin description pin no. 2 fil out amplifies and outputs the sync portion of the video signal input to fil in (pin 69). sync separation circuit input. inputs the fil out (pin 2) output signal via a capacitor. sync separation output. positive polarity output in open collector format. da output. outputs the serial data converted to dc voltage. the current driving capacity is 1.0ma (max.). 2.15v 1.1v sync in sync out da out 3 4 6 symbol pin voltage equivalent circuit description v cc 1 23k 200 gnd1 2 v cc 1 200 gnd1 3 v cc 1 gnd1 4 v cc 1 50 50 gnd1 6 8 f adj connect a resistor between this pin and gnd1 to control the internal lpf and trap frequencies. connect a 33k ? resistor (tolerance 2%, temperature characteristics 200ppm or less). this pin is easily affected by external noise, so make the connection between the pin and external resistor, and between the gnd side of the external resistor and the gnd1 pin as close as possible. 1.1v v cc 1 gnd1 10 6.5k 8
6 CXA3503R pin no. analog 3.0v gnd. gnd1 9 symbol pin voltage equivalent circuit description 14 15 16 sck sen sdat serial clock, serial load and serial data inputs for serial communication. v cc 1 200 gnd1 14 15 16 17 r inject connect a resistor for setting the injector current of the iil logic circuit. connect a 15k ? resistor between this pin and gnd1. use a resistor with a deviation of 2% and temperature characteristics of 200ppm or less. 0.7v 29 gnd2 analog 12.0v gnd. (for the rgb output circuits) v cc 1 200 gnd1 17 30 sig.c r, g and b output dc voltage setting. connect a 0.01f capacitor between this pin and gnd1. when using a sig.c of other than v cc 2/2, input the sig.c voltage from an external source. preset v cc 2/2 variable range: 5.0 to 6.5v v cc 2 gnd1 140k 140k 200 10p 30 31 33 35 b dc det r dc det g dc det smoothing capacitor connection for the feedback circuit of r, g and b output dc level control. connect a low-leakage capacitor. 1.8v v cc 2v cc 1 200 gnd1 31 33 35
7 CXA3503R pin no. symbol pin voltage equivalent circuit description 32 34 36 b out r out g out r, g and b signal outputs. the dc level is controlled to match the sig.c pin voltage. low output in power saving mode. v cc 2/2v output when preset. v cc 2/2 (sig.c = preset) 37 v cc 2 analog 12.0v power supply. (for the rgb output circuits) 12.0v 41 v cc 3 analog 12.0v power supply. (for com output) 12.0v v cc 2 166k 10 10 gnd2 32 34 36 42 com common voltage output. the output voltage is controlled by serial communication. v cc 3 200 gnd3 42 90k 57 58 59 osd b osd r osd g osd pulse inputs. when one of these input pins exceeds the vth1 level, all of the outputs go to black limiter level; when an input pin exceeds the vth2 level, only the corresponding output goes to white limiter level. vth1 = v cc 1 1/3 vth2 = v cc 1 2/3 v cc 1 50k 50k gnd1 57 59 58 43 gnd3 analog 12.0v gnd. (for com output) 69 fil in h filter input. input the video signal via a capacitor. 1.2v 63 v cc 1 analog 3.0v power supply. v cc 1 gnd1 200 69
8 CXA3503R pin no. symbol pin voltage equivalent circuit description 70 71 72 b/b-y g/y r/r-y in y/color difference input mode, input the y signal to pin 71, the b-y signal to pin 70, and the r-y signal to pin 72. in rgb input mode, input the b signal to pin 70, the g signal to pin 71 and the r signal to pin 72. pedestal clamp these pins with external coupling capacitors. g/y 1.8v r/r-y, b/b-y, rgb: 1.8v y/color difference: 2.0v v dd 1 gnd1 200 70 71 72
9 CXA3503R digital block pin description pin no. 1 18 23 53 54 v ss digital 3.0v gnd. 19 20 55 v dd digital 3.0v power supply. 5 14 15 16 csync/hd sck sen sdat composite sync/horizontal sync signal input, and serial clock, serial load and serial data inputs for serial communication. 10 vd vertical sync signal input. 21 22 24 cko cki rpd oscillation circuit output. oscillation circuit input. phase comparator output. symbol pin voltage equivalent circuit description v ss 5 15 16 14 v ss 10 v ss v dd 25 v ss v dd 67 66 68 11 64 65 27 45 46 61 62 26 25 xclr digital block system reset. 11 26 27 45 46 61 62 64 65 66 67 68 vst vdo hdo pof dwn hck1 hck2 hst rgt en stb vck digital block outputs.
10 CXA3503R test pin description pin no. 7 12 13 38 39 40 44 49 50 51 52 tst1 tst2 tst3 tst5 tst6 tst7 tst8 tst11 tst12 tst13 tst14 test. leave these pins open. 28 47 48 56 tst4 tst9 tst10 tst15 test. connect to gnd. symbol pin voltage equivalent circuit description
11 CXA3503R setting conditions for measuring electrical characteristics use the electrical characteristics measurement circuit on page 22 when measuring electrical characteristics. for measurement, the digital block must be initialized and power saving must be canceled by performing settings 1 and 2 below. in addition, the serial data must be set to the initial settings shown in the table below. setting 1. horizontal afc adjustment input a signal and adjust the vco using v22 so that wl and wh of the tp24 output waveform are the same. setting 2. canceling power saving mode the power-on default is power saving mode, so clear (set all "0") serial data ps0, ps1, ps2, ps3, ps4 and sync gen. horizontal sync signal rpd (pin 24) ws wl wh wl wh wl = wh ws fig. 1. horizontal afc adjustment serial data initial settings note) if there is the possibility that data may be set at other than the above-noted addresses, set these data to "0". when using, the address data ? 1 must be set all "0". msb address lsb msb data lsb d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 1 0 1 0 user-bright sub-bright r sub-bright b contrast sub-contrast r sub-contrast b -2 -1 0 0 0 0 0 0 00 com-dc color hue (01000110/lsb) (10001010/lsb) (10001010/lsb) (00111111/lsb) (10011111/lsb) (10011111/lsb) (11111111/lsb) (11111111/lsb) (10000000/lsb) (00000000/lsb) (10000000/lsb) white-limiter (00/lsb) black-limiter (11111/lsb) lpf (000/lsb) 0 0 0 filter (00/lsb) picture-f0 (00/lsb) picture-gain (00000/lsb) 0000 mode (1) da (000/lsb) 0 slrgt (0) sltst0 (0) sltst5 (0) 0 0 0 slsh2 (1) slfl (0) sltst4 (0) 0 0 sync gen (0) slsh1 (1) slfr (0) sltst3 (0) 0 0 ps 4 (0) slsh0 (1) sl4096 (0) sltst2 (0) ps 3 (0) slsys2 (0) slclp2 (0) sldwn (0) ps 2 (0) slsys (1) slclp1 (0) slsyp (1) ps 1 (0) slwd (0) slvdp (0) sltst1 (0) ps 0 (0) slpl (0) slhdp (0) slexvd (0) h-position (10000) hd-position (00000) 0 0 ? 1
12 CXA3503R electrical characteristics ?dc characteristics analog block unless otherwise specified, ta = 25 c, v cc 1 = v dd =3.0v, v cc 2/v cc 3 = 12.0v, sw4 = off for the current consumption measurement, see page 11 for the dac. item current consumption 1 (y/color difference input) current consumption 2 (y/color difference input) current consumption 3 (y/color difference input) current consumption 1 (rgb input) current consumption 2 (rgb input) current consumption 3 (rgb input) current consumption 1 (ps0 = 1) current consumption 2 (ps0 = 1) current consumption 3 (ps0 = 1) current consumption 1 (ps2 = 1) current consumption 1 (ps4 = 1) current consumption 1 (sync gen = 1) current consumption 2 (sync gen = 1) current consumption 3 (sync gen = 1) fil out pin voltage sync in pin voltage sync out pin voltage f adj pin voltage r inject pin voltage sig.c pin voltage b dc det pin voltage r dc det pin voltage g dc det pin voltage fil in pin voltage b/b-y pin voltage 1 b/b-y pin voltage 2 g/y pin voltage r/r-y pin voltage 1 r/r-y pin voltage 2 osd input resistance i1 i2 i3 irgb1 irgb2 irgb3 ips01 ips02 ips03 ips21 ips41 isg1 isg2 isg3 v2 v3 v4 v8 v17 v30 v31 v33 v35 v69 v70 v70 v71 v70 v70 v57 v58 v59 measure the inflow current to pin 63. measure the inflow current to pin 37. measure the inflow current to pin 41. measure the inflow current to pin 63. measure the inflow current to pin 37. measure the inflow current to pin 41. measure the inflow current to pin 63. measure the inflow current to pin 37. measure the inflow current to pin 41. measure the inflow current to pin 63. measure the inflow current to pin 63. measure the inflow current to pin 63. measure the inflow current to pin 37. measure the inflow current to pin 41. during no input during no input during no input during y/color difference input during rgb input during y/color difference input during rgb input 1.8 0.8 0.8 0.4 5.8 1.5 1.5 1.5 0.9 1.7 1.5 1.5 1.7 1.5 80 27.0 3.8 0.90 23.0 3.8 0.90 7.5 0.18 26.5 26.5 7.0 0.18 2.1 1.1 0.2 1.1 0.7 6.0 1.8 1.8 1.8 1.2 2.0 1.8 1.8 2.0 1.8 100 37.0 5.0 1.3 30.0 5.0 1.3 10.0 0.35 1.00 36.5 36.5 9.5 0.35 1.00 2.4 1.4 0.4 1.4 1.0 6.2 2.1 2.1 2.1 1.5 2.3 2.1 2.1 2.3 2.1 120 ma ma ma ma ma ma ma ma a ma ma ma ma a v v v v v v v v v v v v v v v k ? symbol measurement conditions min. typ. max. unit
13 CXA3503R digital block (including some analog block) (ta = 15 to +75 c, v dd = v cc 1 = 3.7 to 3.6v) item high level input voltage low level input voltage high level threshold voltage low level threshold voltage hysteresis voltage high level threshold voltage low level threshold voltage hysteresis voltage high level input current low level input current high level input current low level input current high level input current low level input current high level input current low level input current low level output voltage high level output voltage low level output voltage high level output voltage low level output voltage high level output voltage output leak current v ih v il v t + 1 v t 1 v t+ 1 v t 1 v t + 2 v t 2 v t+ 2 v t 2 | i ih1 | | i il1 | | i ih2 | | i il2 | | i ih3 | | i il3 | | i ih4 | | i il4 | v ol1 v oh1 v ol2 v oh2 v ol4 v oh4 | i oz | schmitt buffer v i = v dd v i = 0v v i = v dd v i = 0v v i = v dd v i = 0v v i = v dd v i = 0v i ol = 1ma i oh = 0.25ma i ol = 2ma i oh = 0.5ma i ol = 1.5ma i oh = 1.25ma high impedance status v dd 0.7 0.6 0.4 0.6 0.2 10 10 2.6 2.6 v dd 0.5 symbol measurement conditions min. 40 40 typ. v dd 0.3 2.6 2.6 1.0 1.0 3.0 100 100 3.0 1.0 2.0 0.3 0.3 0.4 1.0 max. v v v v v v v v a a a a a a a a v v v v v v a unit ? 1 ? 2 ? 3 ? 4 ? 5 ? 6 ? 7 ? 8 ? 9 ? 10 ? 11 applicable pins ? 1 xclr (pin 25), cki (pin 22) ? 2 csync/hd (pin 5), vd (pin 10) ? 3 sck (pin 14), sen (pin 15), sdat (pin 16) ? 4 csync/hd (pin 5), cki (pin 22) ? 5 xclr (pin 25) ? 6 vd (pin 10) ? 7 sck (pin 14), sen (pin 15), sdat (pin 16) ? 8 vst (pin 11), dwn (pin 46), blk (pin 60), rgt (pin 65), en (pin 66), stb (pin 67), vck (pin 68) ? 9 rpd (pin 24), vdo (pin 26), hdo (pin 27), pof (pin 45), hck1 (pin 61), hck2 (pin 62), hst (pin 64) ? 10 cko (pin 21). however, when measuring the output pin (cko), the input level of the input pin (cki) should be 0v or v dd . ? 11 rpd (pin 24)
input sg2 (50mvp-p) to tp71 and measure the output amplitude at tp36. input sg2 (50mvp-p) to tp71 and measure the output amplitude at tp36. assume the output amplitude at tp36 when sg2 (0.5vp-p) is input to tp71 as gmin. ? gcon = g max g min assume the inverted output amplitude at tp36 when sg2 (0.35vp-p) is input to tp71 as vinv, and the non-inverted output amplitude as vninv. ? ginv = 20 log (vninv/vinv) input sg2 (0.35vp-p) to tp71 (tp70, tp72), measure the non-inverted output amplitude at tp32, tp34 and tp36, and obtain the maximum and minimum difference between these values. set cont = 26h, input sg2 (0.35vp-p) to tp71, and assume the non-inverted output amplitude at tp32 and tp34 when sub- cont r/b = 9ah, 00h and ffh as v1, v2 and v3, respectively. ? gsc1 = 20 log (v2/v1) ? gsc2 = 20 log (v3/v1) set u-brt = 1ah and measure the non- inverted level at tp32 and tp34 relative to the non-inverted black level at tp36 when sub-brt r/b = ffh and 00h. set u-brt = ffh, measure the inverted and non-inverted black limit level at tp36 when blk-lim = 00h and 1fh, and assume the difference from the output dc voltage as v bl 1 and v bl 2, respectively. 14 CXA3503R electrical characteristics ac characteristics unless otherwise specified, settings 1 and 2, the serial data initial settings, and the following setting conditions are required. ta = 25 c, v cc 1 = 3.0v, v cc 2 = v cc 3 = 12v, gnd1/2/3 = 0v, v ss = 0v, sw2 = on, sw4 = on, sw32/34/36 = off, no video input, sg1 input to tp5 note: serial data values in the table are hex notation. item symbol serial data setting (hex) measurement conditions min. typ. max. unit maximum gain between input and output y/color difference maximum gain between input and output rgb amount of contrast attenuation inverted and non-inverted gain difference gain difference between r, g and b sub-contrast variable amount sub-bright variable amount black limiter variable amount g max g rgbmax gcon ? g inv ? g rgb 1 ? g rgb 2 ? g sc 1 ? g sc 2 ? v sb 1 ? v sb 2 v bl 1 v bl 2 cont ffh cont ffh mode 00h cont 00h cont 2fh cont 2fh mode 00h cont 2fh sub-cont 00h sub-cont ffh sub-brt r, b 00h sub-brt r, b ffh blk-lim 00h blk-lim 1fh 29 26 25 2.0 0.8 1.6 4.7 32 29 30 5.5 2.7 1.5 1.2 2.1 5.1 34 31 0.3 0.6 0.6 4.5 1.0 2.7 5.4 db db db db db db v v
set cont = ffh, input sg2 (0.35vp-p) to tp71, measure the inverted and non-inverted white limit level when white-lim = 00h and 03h, and assume the difference from the output dc voltage as v wl 1 and v wl 2, respectively. measure the non-inverted black level at tp32, tp34 and tp36, and obtain the maximum and minimum difference between these values. measure the output dc level (average voltage) at tp32, tp34 and tp36 measure the output average voltage difference at tp32 and tp34 relative to the output average voltage at tp36. measure the inverted and non-inverted black level at tp36 when u-brt = 00h and 7ah and assume the difference from the average voltage as ? ub1 and ? ub2, respectively. set u-brt = 23h, cont = 80h, color = 40h, and assume the amplitude at tp32 when sg4 (56mvp-p) is input to tp72 as v1. similarly, assume the amplitude at tp34 when sg4 (100mvp-p) is input to tp70 as v2. = tan 1 (v1/v2). assume the when hue = 00h, 80h and ffh as a, b and c, respectively. 1 = a b, 2 = c b set cont = 2fh, input sg3 to tp71, and measure the tp36 amplitude at f0 relative to the tp36 amplitude at 100khz when pic-g = 01h and 1fh. f0 at pic-f0 = 00h, 01h, 02h and 03h is 2mhz, 2.2mhz, 2.6mhz and 2.9mhz, respectively. input sg4 (50mvp-p) to tp70 and tp72, and assume the output amplitude at tp32 and tp34 when color = 00h, 80h and ffh as v1, v2 and v3, respectively. gc1 = 20 log (v1/v2) gc2 = 20 log (v3/v2) 15 CXA3503R item symbol serial data setting (hex) measurement conditions rgb output dc voltage dc voltage difference between rgb user-brt variable amount hue variable amount picture variable amount color variable amount vc ? vc ? ub1 ? ub2 1 2 gp1 gp2 gc1 gc2 u-brt 00h u-brt 7ah hue 00h hue ffh pic-g 01h pic-g 1fh color 00h color ffh 5.8 4.5 20 20 1.5 10 5.0 6.0 0.8 4.9 25 25 0 12 30 6.0 6.2 200 1.5 1.5 20 v mv v deg deg db db v wl 1 v wl 2 ? v b white-lim 00h white-lim 03h 1.2 0.6 0.6 0 300 v mv white limiter variable amount 1.2 1.8 min. typ. max. unit black level difference between r, g and b
set u-brt = 30h, cont = dfh, input sg7 (13.5mhz) to tp70, tp71 and tp72, and measure the amount by which the output is attenuated when filter = 01h relative to filter = 00h. similarly, input sg7 (14.5mhz) to tp70, tp71 and tp72, and measure the amount by which the output is attenuated when filter = 02h relative to filter = 00h. set sw32, sw34 and sw36 = on, input sg3 to tp70, tp71 and tp72, and measure the frequency which results in 3db relative to the tp32, tp34 and tp36 amplitude at 100khz. measure the da output voltage when da = 00h and 07h. measure under the measurement conditions for each adjustment range. measure under the measurement conditions for each adjustment range. input sg2 (0.35mvp-p) to tp71 and measure the amplitude at tp32, tp34 and tp36. assume the output amplitude when gamma1 = ffh as v1, when gamma1 = 3fh as v2, and when gamma1 = gamma2 = 3fh as v3. ? 1 = 20 log (v1/v2) ? 2 = 20 log (v3/v2) input sg6 to tp69 and measure the output amplitude at tp2. measure the com output dc voltage when com-dc = 00h and ffh, and measure the difference from the com output dc voltage when com-dc = 80h. 16 CXA3503R item symbol serial data setting (hex) measurement conditions trap characteristics frequency response da adjustment range internal dac differential non-linearity error internal dac non-linearity error gamma characteristics h fil gain fo1 fo2 f rgb vda1 vda2 sdl sl ? 1 ? 2 ghfil mode 00h mode 00h mode 00h da 00h da 07h cont 41h 5.5 2.7 1.5 2.0 12 12 15.0 27 27 14 14 17.0 20 20 0.3 1.5 2.0 16 16 db mhz v lsb lsb db db output current 1.0ma output current 1.0ma assume the tp34 output when sg4 (0.1vp-p) is input to tp72 as rr, the tp32 amplitude when sg4 (0.1vp-p) is input to tp70 as bb, the tp34 amplitude when sg5 (0.1vp-p) is input to tp72 as rg, and the tp32 amplitude when sg5 (0.1vp-p) is input to tp70 as bg. b-y/r-y = rr/bb, g-y/r-y = rg/rr, g-y/b-y = bg/bb input sg3 to tp71 and measure the frequency which results in 3db relative to the tp36 amplitude at 100khz when lpf = 01h and 07h. b-y/ r-y g-y/ r-y g-y/ b-y fc1 fc2 cont 63h color 6fh lpf 01h mode 00h lpf 07h mode 00h 0.85 0.41 0.15 5.0 1.00 0.51 0.19 2.0 6.4 1.15 0.61 0.23 2.5 mhz matrix amplitude ratio lpf characteristics min. typ. max. unit common control range com dc 1.0 1.3 v
input sg4 to tp57, tp58 and tp59, gradually raise the high level from 0v, and assume the high level voltage at which the output level goes to blk-lim level as vth1osd, and the high level voltage at which the output level goes to white-lim level as vth2osd. set sw32, sw34 and sw36 = on, input sg4 (0.35vp-p) to tp71, and measure the propagation delay time of the non- inverted output rise and fall at tp32, tp34 and tp36 from tp71. set sw32, sw34 and sw36 = on, input sg4 (0.35vp-p) to tp70, tp71 and tp72, and measure the propagation delay time of the non-inverted output rise and fall at tp32, tp34 and tp36 from tp70, tp71 and tp72. set sw32, sw34 and sw36 = on, input sg4 (0.35vp-p) to tp71, and measure the propagation delay time of the non- inverted output rise and fall at tp32, tp34 and tp36 from tp71. set sw32, sw34 and sw36 = on, input sg4 (3vp-p) to tp57, tp58 and tp59, and measure the propagation delay time of the non-inverted rise and fall at tp70, tp71 and tp72 from tp57, tp58 and tp59. input sg6 to tp69 and measure the propagation delay time of the rise and fall at tp2 from tp69. set sw2 = off, input sg8 to tp3, and measure the propagation delay time of the rise and fall at tp4 from tp3. gradually increase the sync in outflow current and measure the current at which sync out switches to high. measure the sync out pin voltage during sync in no input. 17 CXA3503R item symbol serial data setting (hex) measurement conditions osd threshold value propagation delay time between input and output y/color difference 1 propagation delay time between input and output rgb input propagation delay time between input and output y/color difference 2 propagation delay time between osd input and output propagation delay time between h fil and fil out propagation delay time between sync in and sync out vth1 osd vth2 osd tlh1 thl1 tlh2 thl2 tlh3 thl3 tlh4 thl4 tlh7 thl7 tlh8 thl8 mode 00h pic-g 01h sen setup time, activated by the rising edge of sck. (see fig. 4.) sdat setup time, activated by the rising edge of sck. (see fig. 4.) 0.8 1.8 70 80 60 60 270 270 90 170 500 100 140 40 1.0 2.0 120 130 110 110 330 330 130 210 700 300 200 100 1.2 2.2 170 180 160 160 390 390 170 250 900 500 260 160 v ns ns ns ns ns ns data setup time ts0 ts1 150 150 ns sync in sensitivity current sync out on voltage i sync vosync 20 31 0.2 0.4 a v min. typ. max. unit
18 CXA3503R data hold time minimum pulse width output transition time cross-point time difference hck duty th0 th1 tw1l tw1h tw2 ? t dtyhc sen hold time, activated by the rising edge of sck. (see fig. 4.) sdat hold time, activated by the rising edge of sck. (see fig. 4.) sck pulse width. (see fig. 4.) sck pulse width. (see fig. 4.) sen pulse width. (see fig. 4.) measure the transition time of each output. 30pf load: vdo, hdo and pof output pins 40pf load: rpd, hck1, hck2 and hst output pins (see fig. 2.) measure the transition time of each output. 40pf load: vst, dwn, blk, rgt, en, stb and vck output pins (see fig. 2.) measure hck1/hck2. 120pf load (see fig. 3.) measure the hck1/hck2 duty. 120pf load 50 10 53 ns ns ns s ns ns ns % 150 150 210 210 1 47 item symbol serial data setting (hex) measurement conditions 30 ttlh 30 50 50 tthl ttlh tthl min. typ. max. unit
19 CXA3503R electrical characteristic measurement method diagrams ttlh 90% 10% tthl 50% ? t ? t fig. 2. output transition time measurement conditions fig. 3. cross-point time difference measurement conditions fig. 4. serial transfer block measurement conditions d15 sdta sck sen ts1 th1 tw1h tw1l th0 tw2 ts0 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d15 50% 50%
20 CXA3503R sg no. sg1 sg2 sg3 sg4 sg5 waveform 1h 3.0vp-p horizontal sync signal (csync) 4.7 s 1h amplitude variable horizontal sync signal 0.1vp-p 0.1vp-p 1h high level variable 0v horizontal sync signal 25 s10 s 25 s 10 s 3v low level variable horizontal sync signal sine wave video signal; frequency and amplitude variable
21 CXA3503R sg no. sg6 waveform 1h 50mvp-p horizontal sync signal (csync) 4.7 s sg7 0.1vp-p 1h sine wave video signal sg8 1h 0.15vp-p horizontal sync signal (csync) 4.7ns
22 CXA3503R electrical characteristics measurement circuit ? 1 resistance value tolerance: 2%, temperature coefficient: 200ppm or less locate this resistor as close to the ic pin as possible to reduce the effects of external signals. ? 2 varicap diode: 1t369 (sony) vss fil out sync in sync out csync/hd g out g dc det r out r dc det b out b dc det sig.c gnd2 tst4 hdo xclr vdo rpd vss cki cko v dd v dd v dd tst15 osd b osd r osd g blk hck1 hck2 vcc1 hst rgt en stb vck fil in b/b-y g/y r/r-y vss vss tst14 tst13 tst12 tst11 tst10 tst9 dwn pof tst8 gnd3 com vcc3 tst7 tst6 tst5 vcc2 +3v +12v v22 0.01 3.9 220p 6800p 33k 1k tp24 10k 3.3 0.01 47 +12v 1 47 +12v 1 47 1 47 39p 10k ? 2 0.1 0.01 0.1 0.1 1 sw2 tp6 tp14 tp15 tp16 tp3 1k sw4 tp2 0.1 10 +3v 0.01 47 tp57 tp69 tp70 tp71 tp72 tp58 tp42 tp30 tp59 1 0.01 0.01 0.01 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 61 62 63 64 65 66 67 68 69 70 71 72 1 2 3 4 da out tst1 f adj gnd1 vd vst tst2 tst3 sck sen sdat r inject v ss ? 1 15k 33k tp5 tp4 6 7 8 9 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 33 35 36 a a a a a 300p sw36 tp36 10 300p sw34 tp34 10 300p sw32 tp32 34 32 5 10 tp45 tp27 tp26 ? 1 tp11 tp68 tp67 tp66 tp65 tp64 tp61 tp60 tp62 60
23 CXA3503R description of operation 1) rgb and y/color difference signal processing block signal processing is comprised of picture, hue, matrix, lpf/trap, contrast, osd, sample-and-hold, correction, bright, sub-bright, sub-contrast and output circuits input signal mode switching the input mode (rgb input, y/color difference input) can be switched by the serial communication settings. (during internal sync separation signal input) during rgb input: the g signal is input to pins 71 and 69, the b signal to pin 70, and the r-y signal to pin 72. during y/color difference input: the y signal is input to pins 71 and 69, the b-y signal to pin 70, and the r-y signal to pin 72. (during external sync signal input) during rgb input: the g signal is input to pin 71, the b signal to pin 70, the r signal to pin 72, csync/hd to pin 5, and vd to pin 10. during y/color difference input: the y signal is input to pin 71, the b-y signal to pin 70, the r-y signal to pin 72, csync/hd to pin 5, and vd to pin 10. ntsc/pal switching the input system (ntsc/pal) can be switched by the serial communication settings. picture circuit this performs aperture correction for the y signal. the center frequency to be corrected and the correction amount are controlled by serial communication. in addition, when not using the picture circuit, it can be turned off by serial communication. hue circuit this is the hue adjustment circuit for the color difference signal. it is controlled by serial communication. matrix circuit this circuit converts y, r-y and b-y signals into rgb signals. lpf circuit this is the band limitation filter for the rgb signal. it is used to eliminate the noise component generated at the front end of this ic. the cut-off frequency can be controlled by serial communication. in addition, when not using the lpf, it can be turned off by serial communication. trap circuit this is used to eliminate the dsp clock and rgb decoder carrier leak generated at the front end of this ic. the center frequency can be switched between 13.5mhz and 14.3mhz by serial communication. in addition, when not using the trap, it can be turned off by serial communication. contrast adjustment circuit this adjusts the white-black amplitude to set the input rgb signal to the appropriate output level. osd this inputs the osd pulses. there are two input threshold values: vth1 (v cc 1 1/3) and vth2 (v cc 1 2/3). when an input exceeds vth1, the corresponding output falls to the level specified by black-limite. when an input exceeds vth2, the corresponding output rises to the level specified by white-limiter. also, when one of the rgb inputs exceeds vth1, any signal outputs not exceeding vth1 also fall to the level specified by black-limiter.
24 CXA3503R sample-and-hold circuit this circuit performs time axis correction for the rgb output signals in order to support the rgb simultaneous sampling systems of lcd panels. hck1 a a' b' b c c' s/h1 s/h4 s/h2 s/h4 s/h3 sh3 sh4 sh2 sh1 s/h4 r g b r g b the sample-and-hold circuit performs sample-and-hold by receiving the sh1 to sh4 pulses from the tg block. since lcd panels perform color coding using an rgb delta arrangement, each horizontal line must be compensated by 1.5 dots. this relationship is reversed during right/left inversion. this compensation and other timing is also generated by the digital block. the sample-and-hold timing changes according to the phase relationship with the hck pulse, so the timing should be set to the shs1, 2 or 6 position in accordance with the actual board. correction in order to support the characteristics of lcd panels, the i/o characteristics are as shown in fig. 1. the 1 gain transition point a voltage changes as shown in fig. 2 by adjusting the serial bus register 1, and the 2 gain transition point b voltage changes as shown in fig. 3 by adjusting 2. output input b b" a' a output input b b' a output input fig. 1 fig. 2 fig. 3 b a sh1 sh2 sh3 sh4 shs1 b a through c shs2 a' c' through b' shs3 a c through b shs4 c' b' through a' shs5 c b through a shs6 b' a' through c' rgt = l (right/left inversion) sh1 sh2 sh3 sh4 shs1 b through a c shs2 a' through c' b' shs3 a through c b shs4 c' through b' a' shs5 c through b a shs6 b' through a' c' rgt = h (normal) sh1: r signal sh pulse sh2: g signal sh pulse sh3: b signal sh pulse sh4: rgb signal sh pulse shs1, 2, 3, 4, 5, 6: serial data settings
25 CXA3503R bright circuit this is used to adjust the black-black amplitude of polarity-inverted rgb output signals. it is not interlinked with the transition points. white balance adjustment circuit this is used to adjust the white balance. the black level is adjusted by sub-bright, and the black-white amplitude is adjusted by sub-contrast. output circuit rgb output (pins 70, 71, and 72) signals are inverted each horizontal line by the frp pulse (internal pulse) supplied from the tg block as shown in the figure below. feedback is applied so that the center voltage (sig.c) of the output signal matches the reference voltage (v cc 2 + gnd2)/2 (or the voltage input to sig.c (pin 30)). in addition, the white level output is clipped at the limiter operation point that is set by the serial communication white-limiter, and the black level output is clipped at the limiter operation point that is set by the serial communication black-limiter. during 16:9 display the rgb output is specified by black-limiter level at a certain timing and goes to black-limiter level output. black-limiter sig.c white-limiter white-limiter black-limiter set by black-limiter rgb in 1h inverted signal (internal) 16:9 display signal (internal) rgb out
26 CXA3503R 2) common voltage generation circuit block the common voltage circuit generates and supplies the common pad voltage to the lcd panel. the voltage is offset by serial communication using the sig.c voltage as the reference and then output. 3) dac output circuit there are two dac output circuit systems. the da out output circuit outputs dc 3.0v at equal divisions and is controlled by serial communication. 4) sync system h fil this amplifies the sync signal of the input video signal and eliminates the noise with an internal lpf. the sync signal is clamped at the input, so be sure to input via a capacitor. sync sep this inputs the fil out (pin 2) output and performs sync separation. the signal is output from sync out (pin 4) as a positive polarity pulse. 5) power saving circuit (ps circuit) a power saving system can be realized together with the lcd panel by independently controlling (serial communication) the operation of each output block. this system is also effective for improving picture quality during power-on/off. the serial data ps0, ps1, ps2, ps3, ps4 and sync gen must be set in order to use this ic. for details of the setting methods, see the "description of serial control operation" and "power supply and power saving sequence" items.
27 CXA3503R 6) tg block pll and afc circuits a pll circuit can be comprised by connecting a pll circuit phase comparator and frequency division counter and external vco and lpf circuits. the pll error detection signal is generated using the phase comparison output of the entire bottom of the horizontal sync signal and the internal frequency division counter as the rpd output. rpd output is converted to dc error voltage with the lag-lead filter, and then it changes the capacitance of the varicap diode to stabilize the oscillation frequency. the pll of this system is adjusted by setting the reverse bias voltage of the varicap diode so that the point at which rpd changes is at the center of the horizontal sync signal window as shown in the figure below. horizontal sync signal rpd (pin 24) ws wl wh wl wh wl = wh ws h-position this adjusts the horizontal display position. set this function so that the picture center matches the center of the lcd panel. right/left (rgt) and/or up/down inversion (dwn) the video display direction can be switched. the horizontal direction can be switched between right scan and left scan, and the vertical direction between down scan and up scan. set the display direction in accordance with the lcd panel mounting position. wide mode 16:9 quasi-wide display can be achieved by converting the aspect ratio through pulse elimination processing. during wide mode, vertical pulse elimination scanning is performed for both ntsc and pal display and the video signal is compressed to achieve a 16:9 aspect ratio. in addition, in areas outside the display area, the black level set by black-limiter (serial communication data) is wide-masked as the black signal within the limited vertical blanking period. this function achieves a quasi-display by simply pulse eliminating the video signal, so some video information is lost. display area display area black display area pulse elimination display black display black display area 16:9 display 4:3 display 172 lines 228 lines 28 lines 28 lines ac driving of lcd panels during no signal the output signal runs freely so that the lcd panel is ac driven even when there is no sync signal from the fil in (pin 69) pin or from the csync/hd (pin 5) and vd (pin 10) pins. during this time, the sync separation circuit stops and the auxiliary counter is used to generate the free running output pulses after detecting that there is no vertical sync signal for approximately 3 fields (no signal state).
28 CXA3503R description of serial control operation 1) control method control data consists of 16 bits of data which is loaded one bit at a time at the rising edge of sck. this loading operation starts from the falling edge of sen and is completed at the next rising edge. digital block control data is established by the vertical sync signal, so if data is transferred multiple times for the same item, the data immediately before the vertical sync signal is valid. analog (electronic attenuator) block control data becomes valid each time the sen signal is input. in addition, if 16 bits of more of sck are not input while sen is low, the transferred data is not loaded to the inside of the ic and is ignored. if 16 bits or more of sck are input, the 16 bits of data before the rising edge of the sen pulse are valid data. sdat a7a6a5a4a3a2a1a0d7d6d5d4d3d2d1d0 sck sen d: data a: address serial transfer timing 2) serial data map the serial data map is as follows. values inside parentheses are the default values. note) if there is the possibility that data may be set at other than the above-noted addresses, set these data to "0". when using, the address data ? 1 must be set all "0". msb address lsb msb data lsb d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 1 0 1 0 user-bright sub-bright r sub-bright b contrast sub-contrast r sub-contrast b -2 -1 (0) (1) (0) (0) (0) (0) (0) (0) com-dc color hue (10000000/lsb) (10000000/lsb) (10000000/lsb) (10000000/lsb) (10000000/lsb) (10000000/lsb) (00000000/lsb) (00000000/lsb) (10000000/lsb) (00000000/lsb) (10000000/lsb) white-limiter (00/lsb) black-limiter (10000/lsb) lpf (000/lsb) (0) (1) (1) filter (00/lsb) picture-f0 (00/lsb) picture-gain (00000/lsb) (0) (0) (0) (0) mode (0) da (000/lsb) (0) slrgt (0) sltst0 (0) sltst5 (0) (0) (0) (0) slsh2 (0) slfl (0) sltst4 (0) (0) (0) sync gen (1) slsh1 (0) slfr (0) sltst3 (0) (0) (0) ps 4 (1) slsh0 (0) sl4096 (0) sltst2 (0) ps 3 (1) slsys2 (0) slclp2 (0) sldwn (0) ps 2 (1) slsys1 (0) slclp1 (0) slsyp (0) ps 1 (1) slwd (0) slvdp (0) sltst1 (0) ps 0 (1) slpl (0) slhdp (0) slexvd (0) h-position (10000/lsb) hd-position (00000/lsb) (0) (0) ? 1
29 CXA3503R 3) description of control data user-bright this adjusts the brightness of the rgb output signals. adjustment from lsb msb increases the amplitude (black-black). sub-bright r/b this adjusts the brightness of the r and b output signals using the g output signal as the reference. adjustment from lsb msb increases the amplitude (black-black). contrast this adjusts the contrast of the rgb output signals. adjustment from lsb msb increases the amplitude (black-white). sub-contrast r/b this adjusts the contrast of the r and b output signals using the g output signal as the reference. adjustment from lsb msb increases the amplitude (black-white). -2 this sets the white side point level of the rgb output signals. adjustment from msb lsb lowers the point. when not adjusting -2, set -2: 11111111 (lsb). set the -2 point to the white side of the -1 point. -1 this sets the black side point level of the rgb output signals. adjustment from msb lsb lowers the point. when not adjusting -1, set -1: 11111111 (lsb). set the -1 point to the black side of the -2 point. com-dc this adjusts the common output voltage. adjustment from lsb msb increases the output voltage. color this adjusts the color gain during y/color difference input. adjustment from lsb msb increases the gain. hue this adjusts the phase during y/color difference input. adjustment from lsb msb advances the phase. white-limiter this adjusts the white side limiter level of the rgb output signals. see the ac characteristics for the output level. black-limiter this adjusts the black side limiter level of the rgb output signals. adjustment from lsb msb lowers the limiter level.
30 CXA3503R lpf this switches the frequency response of the low-pass filter. set the fc/ 3db frequency relative to the amplitude 100khz reference. see the ac characteristics for the output level. d1 0 0 1 1 0 0 1 1 d0 0 1 0 1 0 1 0 1 d2 0 0 0 0 1 1 1 1 fc (rgb input/no load/typ.) lpf off 2.0mhz 2.7mhz 3.4mhz 3.9mhz 4.9mhz 5.7mhz 6.4mhz filter this sets the trap (f0) center frequency. see the ac characteristics for the output level. d6 0 1 0 1 d7 0 0 1 1 center frequency (f0) trap off 13.5mhz 14.3mhz picture-f0 this sets the picture center frequency (f0) during y/color difference input. see the ac characteristics for the output level. d0 0 1 0 1 d1 0 0 1 1 center frequency (f0) 2.0mhz (typ.) 2.2mhz (typ.) 2.6mhz (typ.) 2.9mhz (typ.) picture-volume this adjusts the picture gain during y/color difference input. adjustment from lsb msb raises the gain. when not using the picture function (off), set picture-volume: 00000 (lsb). da this adjusts the da output voltage. see the ac characteristics for the output level.
31 CXA3503R sync gen this sync generator mode stops all output pulses other than the hdo and vdo output pulses. the ps0, ps1, ps2, ps3 and ps4 settings have priority over the sync gen setting. normally set to "0". d5 0 1 mode (sync gen) normal operation all output pulses and corresponding output blocks other than the hdo and vdo output pulses are stopped. ps0, ps1, ps2, ps3, ps4 these perform the power saving settings for each input and output block. be sure to use these settings as described in "power supply and power saving sequence". the power-on default for this ic is power saving mode, so the settings should be canceled by serial communication after power-on. d0, 1, 2, 4 0 1 mode (ps0, ps1, ps2, ps3, ps4) normal operation the respective outputs and corresponding output blocks are stopped. mode this switches the input signal. d3 0 1 input signal rgb input y/color difference input
32 CXA3503R fig. 2. system block diagram power supply and power saving sequence when using this ic, the power supply sequences described below must be followed during power-on/off to ensure reliability as a lcd driving system. thoroughly study the function specifications of each control method (1), (2) and (3) before use. control timing (1) use this timing when not using the power saving (ps) function regardless of picture quality during power- on/off. control timing (2) use this timing when using the power saving (ps) function regardless of picture quality during power-on/off. control timing (3) use this timing when using the power saving (ps) function and placing priority on picture quality during power-on/off. control timing (1) (1) ic power-on (3v, 12v), lcd power-on (hv dd , vv dd ) (2) a settings: after the ic and lcd power supplies have risen (3) ic power-off (3v, 12v), lcd power-off (hv dd , vv dd ): optional the lcd power supply (hv dd , vv dd ) rise timing should adequately satisfy the panel specifications. serial data settings other than ps should be made during the control period from the rise of the ic 3v power supply to (2). ? 1 during ic power-on (default status), the ps mode is activated (the ps0, ps1, ps2, ps3, ps4 and sync gen data are all set to "1"). therefore, the ps settings should be canceled via serial communication in accordance with the sequence specifications. ? 2 when inputting the sync signal from an external source, set serial data ps4 = 1. ? 3 when using this control timing, set serial data ps2 = 0. lcd power supply ic 12v ic 3v sync gen circuit ps4 circuit ps3 circuit ps1 circuit ps0 circuit default lcd display fig. 1 ps off power-on power-off ? 1 ? 1 ? 2 ? 2 default lcd display ps off power-on power-off status supply voltage & output signal operation power-on/off & ps settings (serial data) ? 3 ic power-on lcd power-on a ps0 0 ps1 0 ps3 0 ps4 0 (1) sync gen 0 ic power-on lcd power-on ic power-off lcd power-off ic power-off lcd power-off a ps0 0 ps1 0 ps3 0 ps4 0 (1) sync gen 0 v cc /v dd CXA3503R lcd signal hv dd / vv dd power supply
33 CXA3503R control timing (2) (1) ic power-on (3v, 12v), lcd power-on (hv dd , vv dd ) (2) a settings: after the ic and lcd power supplies have risen (3) b settings: optional (4) ic power-off (3v, 12v), lcd power-off (hv dd , vv dd ): optional it is possible to skip from step (2) to step (4) without making the b settings (dotted lines in the figure). the lcd power supply (hv dd , vv dd ) rise timing should adequately satisfy the panel specifications. serial data settings other than ps should be made during the control period from the rise of the ic 3v power supply to (2). ? 1 during ic power-on (default status), the ps mode is activated (the ps0, ps1, ps2, ps3, ps4 and sync gen data are all set to "1"). therefore, the ps settings should be canceled via serial communication in accordance with the sequence specifications. ? 2 when inputting the sync signal from an external source, set serial data ps4 = 1. ? 3 when using this control timing, set serial data ps2 = 0. lcd power supply ic 12v ic 3v sync gen circuit ps4 circuit ps3 circuit ps1 circuit ps0 circuit fig. 1 ps on ? 1 ? 2 ? 2 ps ps (default) lcd display lcd display ps ps off ps off power-off power-on ps on ic power-on lcd power-on a ps0 0 ps1 0 ps3 0 ps4 0 (1) sync gen 0 sync gen 1 ic power-off lcd power-off a ps0 0 ps1 0 ps3 0 ps4 0 (1) b ps0 1 ps1 1 ps3 1 ps4 1 b ps0 1 ps1 1 ps3 1 ps4 1 sync gen 0 sync gen 1 status supply voltage & output signal operation power-on/off & ps settings (serial data) ? 3 v cc /v dd CXA3503R lcd signal hv dd / vv dd power supply fig. 2. system block diagram
34 CXA3503R control timing (3) (1) ic power-on (3v) (2) ic power-on (12v), lcd power-on (hv dd , vv dd ): after the ic power supply (3v) has completely risen (3) a settings: after the ic (12v) and lcd power supplies have risen (4) b se ttings: after the pll has stabilized (stable rpd waveform) and the panel i/o power supply conditions have been satisfied. (5) c settings: optional (6) d settings: after com and rgb have fallen (7) e settings: 100ms or more after the d settings (8) ic power-off (12v), lcd power-off (hv dd , vv dd ): after the hv dd and vv dd pin voltages have fallen (9) ic power-off (3v): after the ic power supply (12v) has completely fallen serial data settings other than ps should be made during the control period from the rise of the ic 3v power supply to (3). the lcd power supply (hv dd , vv dd ) rise timing should adequately satisfy the panel specifications. ? 1 during ic power-on (default status), the ps mode is activated (the ps0, ps1, ps2, ps3, ps4 and sync gen data are all set to "1"). therefore, the ps settings should be canceled via serial communication in accordance with the sequence specifications. ? 2 when inputting the sync signal from an external source, set serial data ps4 = 1. ? 3 when raising the power supplies, first raise the ic 3v power supply, then raise the ic 12v and lcd power supplies. ? 4 when lowering the power supplies, first lower the lcd and ic 12v power supplies, then lower the ic 3v power supply. ? 5 when using this control timing, set serial data ps2 = 0. lcd power supply ic 12v ic 3v sync gen circuit ps4 circuit ps3 circuit ps1 circuit ps0 circuit fig. 1 ps on ? 1 ? 3 ? 4 ? 2 ? 2 ps ps (default) lcd display lcd display ps ps off ps off power-off power-on ps on ic power-on lcd power-on a ps0 0 ps1 0 ps3 0 ps4 0 sync gen 1 b ps0 0 ps1 0 ps3 0 ps4 0 (1) sync gen 0 c ps0 1 ps1 0 ps3 0 ps4 0 (1) sync gen 0 d ps0 1 ps1 1 ps3 0 ps4 0 (1) sync gen 0 c ps0 1 ps1 0 ps3 0 ps4 0 (1) sync gen 0 d ps0 1 ps1 1 ps3 0 ps4 0 (1) sync gen 0 e ps0 1 ps1 1 ps3 1 ps4 1 sync gen 1 e ps0 1 ps1 1 ps3 1 ps4 1 sync gen 1 ic power-off lcd power-off a ps0 0 ps1 0 ps3 0 ps4 0 sync gen 1 b ps0 0 ps1 0 ps3 0 ps4 0 (1) sync gen 0 status supply voltage & output signal operation power-on/off & ps settings (serial data) ? 5 v cc /v dd CXA3503R lcd signal hv dd / vv dd power supply fig. 2. system block diagram
35 CXA3503R slpl this switches the display system. d0 0 1 display system ntsc pal slwd this switches the display aspect. d1 0 1 supported aspect 4:3 display 16:9 display slrgt this is the right/left inversion function. this switches the horizontal scan direction of the lcd panel. d7 0 1 scan mode normal display (right scan) right/left inverted display (left scan) slsys1, 2 these switch the supported panel. d2 0 1 0 1 d3 0 0 1 1 supported panel lcx032ak lcx033ak slsh0, slsh1, slsh2 these switch the sample-and-hold timing. slsh2 d6 0 0 0 0 1 1 1 1 slsh1 d5 0 0 1 1 0 0 1 1 slsh0 d4 0 1 0 1 0 1 0 1 sample-and-hold position shs1 shs2 shs3 shs4 shs5 shs6 through (sample-and-hold off) through (sample-and-hold off)
36 CXA3503R slfl this function is used to stop output signal polarity inversion. normally set to polarity inversion. d6 0 1 mode polarity inversion polarity inversion stopped slhdp, slvdp these switch the hdo output and vdo output polarity. d0 0 1 output polarity (hdo) positive polarity negative polarity slfr this function inverts the output signal polarity every field. normally set to 1h inversion. d5 0 1 mode 1h inversion 1 field inversion d1 0 1 output polarity (vdo) positive polarity negative polarity slcp1, slcp2 these switch the clamp position. d2 0 1 0 1 d3 0 0 1 1 clamp position a (back porch position/when using the internal sync separation signals) b (sync position/when using the internal sync separation signals) c (back porch position/during external sync signal input) d (sync position/during external sync signal input) 2.35 s sync rpd xclp b a c d 1.3 s 1 s 2.35 s 2 s 2.9 s 2 s 2 s 2 s 3.6 s sl4096 this function inverts the output signal polarity every 4096 fields. this further inverts the polarity of the rgb output that is inverted every 1h for 4096 fields. normally set to 1h inversion. d4 0 1 mode 1h inversion 1h inversion + 4096 field inversion note) when clamp is performed at back porch and sync position, set back porch and sync period of pins 69, 70, 71 and 72 input signals at pedestal level.
37 CXA3503R sltst0, 1, 2, 3, 4, 5 these are the test functions. set to normal mode. hp1, 2, 3, 4, 5 these set the h position. the horizontal display position is switched by adjusting the hst pulse position using the input horizontal sync signal as the reference. adjustment is possible in 1 bit = 2fh increments. (1fh = 1 dot) d0, 1, 2 0 1 mode normal mode test mode horizontal sync signal hst hp: 11111 (lsb) hp: 10000 (lsb) hp: 00000 (lsb) 15 steps (30fh) 16 steps (32fh) slsyp this switches the input sync polarity. when using the pin 4 (sync out) output as the sync signal (when using the internal sync separation signals), set this to "0". d2 0 1 input polarity positive polarity negative polarity sldwn this is the up/down inversion function. this switches the vertical scan direction of the lcd panel. d3 0 1 scan mode normal display (down scan) up/down inverted display (up scan) slexvd this switches the external vertical sync signal (vd/pin 10) input. this is used when not performing sync separation with the internal sync separation circuit during external separate sync (vd, hd/pins 10 and 5) input. set to "0" during external csync/pin 5 input. d0 0 1 mode other than during external vertical sync signal input external vertical sync signal input
38 CXA3503R hdp1, 2, 3, 4, 5 these set the hdo output pulse position. the hdo pulse output position is switched using the input horizontal sync signal as the reference. adjustment is possible in 1 bit = 4fh increments. (1fh = 1 dot) horizontal sync signal hdo hdp: 00000 (lsb) hdp: 11111 (lsb) 31 steps (124fh)
39 CXA3503R application circuit (rgb input/y/color difference input, during internal sync separation signal input) ? 1 resistance value tolerance: 2%, temperature coefficient: 200ppm or less locate this resistor as close to the ic pin as possible to reduce the effects of external signals. ? 2 varicap diode: 1t369 (sony) ? 3 connect to gnd when not using osd input. ? 4 l: 3.9 h c: 39pf (lcx033), l: 10 h c: 20pf (lcx032) 1 270 1 vss fil out sync in sync out csync/hd da out tst1 f adj gnd1 vd vst tst2 tst3 sck sen sdat r inject v ss g out g dc det r out r dc det b out b dc det sig.c gnd2 tst4 hdo xclr vdo rpd vss cki cko v dd v dd v dd tst15 osd b osd r osd g blk hck1 hck2 vcc1 hst rgt en stb vck fil in b/b-y g/y r/r-y vss vss tst14 tst13 tst12 tst11 tst10 tst9 dwn pof tst8 gnd3 com vcc3 tst7 tst6 tst5 vcc2 +3v 0.01 l 220p 6800p 33k 1k 10k 3.3 0.01 47 +12v 1 47 +12v 1 47 47 to lcd panel c 10k 47k ? 2 ? 1 ? 1 ? 4 ? 4 ? 3 0.1 0.01 0.68 10 0.68 15k 33k 1k 10 0.68 10 +3v 0.01 47 0.01 0.01 0.01 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 +3v 1 47 to serial controller to lcd panel to lcd panel to lcd panel b/b-y g/y r/r-y +12v application circuits shown are typical examples illustrating the operation of the devices. sony cannot assume responsibility fo r any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same .
40 CXA3503R application circuit (rgb input/y/color difference input, during external sync signal input) ? 1 resistance value tolerance: 2%, temperature coefficient: 200ppm or less locate this resistor as close to the ic pin as possible to reduce the effects of external signals. ? 2 varicap diode: 1t369 (sony) ? 3 connect to gnd when not using osd input. ? 4 during csync input, input to pin 5 only (leave pin 10 open). during separate sync (hd, vd) input, input to pins 5 and 10. ? 5 l: 3.9 h c: 39pf (lcx033), l: 10 h c: 20pf (lcx032) vss fil out sync in sync out csync/hd da out tst1 f adj gnd1 vd vst tst2 tst3 sck sen sdat r inject v ss g out g dc det r out r dc det b out b dc det sig.c gnd2 tst4 hdo xclr vdo rpd vss cki cko v dd v dd v dd tst15 osd b osd r osd g blk hck1 hck2 vcc1 hst rgt en stb vck fil in b/b-y g/y r/r-y vss vss tst14 tst13 tst12 tst11 tst10 tst9 dwn pof tst8 gnd3 com vcc3 tst7 tst6 tst5 vcc2 +3v 0.01 l 220p 6800p 33k 1k 10k 3.3 0.01 47 +12v 1 47 +12v 1 47 47 to lcd panel c 10k 47k ? 2 ? 1 ? 1 ? 4 0.1 0.01 0.68 10 0.68 15k 33k 100k csync/hd vd 10 0.68 10 +3v 0.01 47 0.01 0.01 0.01 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 +3v 1 47 to serial controller to lcd panel to lcd panel to lcd panel b/b-y g/y r/r-y +12v ? 3 ? 5 ? 5 application circuits shown are typical examples illustrating the operation of the devices. sony cannot assume responsibility fo r any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same .
41 CXA3503R notes on operation (1) this ic contains digital circuits, so the set board pattern must be designed in consideration of undesired radiation, interference to analog circuits, etc. care should also be taken for the following items when designing the pattern. the digital and analog ic power supplies should be separated, but the gnd and v ss should not be separated and should use a plain gnd (v ss ) pattern in order to reduce impedance as much as possible. the power supplies should also use a plain pattern. use ceramic capacitors for the by-pass capacitors between the power supplies and gnd, and connect these capacitors as close to the pins as possible. the resistor connected to pin 8 should be connected as close to the pin as possible, and the wiring from the pin to gnd should be as short as possible. also, do not pass other signal lines close to this pin or the connected resistor. the resistor connected to pin 17 should be located as close to the pin as possible. also, do not pass other signal lines close to this pin. the capacitors connected to pin 42 should be located as close to the lcd panel as possible. the pll block (lpf/vco) should be compact and located near the ic. (2) the r/r-y (pin 72), g/y (pin 71), b/b-y (pin 70) and fil in (pin 69) pin input signals are clamped at the inputs using the capacitors connected to each pin, so these signals should be input at sufficiently low impedance. (input at an impedance of 1k ? (max.) or less.) (3) the smoothing capacitor of the dc level control feedback circuit in the capacitor block connected to the rgb output pins should have a leak current with a small absolute value and variance. also, when using the pulse elimination (pal display, wide display) function, the picture quality should be thoroughly evaluated before deciding the capacitance value of the capacitor. (4) a thorough study of whether the capacitor connected to the com output pin satisfies the lcd panel specifications should be made before deciding the capacitance value. (5) if this ic is used in connection with a circuit other than an lcd, it may cause that circuit to malfunction depending on the order in which power is supplied to the circuits. thoroughly study the consequences of using this ic with other circuits before deciding on its use. (6) since this ic utilizes a c-mos structure, it may latch up due to excessive noise or power surge greater than the maximum rating of the i/o pins, or due to interface with the power supply of another circuit, or due to the order in which power is supplied to circuits. be sure to take measures against the possibility of latch up. (7) be sure to observe the power supply and power saving sequence specifications specified for this ic. (8) do not apply a voltage higher than v dd or lower than v ss to i/o pins. (9) do not use this ic under operating conditions other than those given. (10) absolute maximum rating values should not be exceeded even momentarily. exceeding ratings may damage the device, leading to eventual breakdown. (11) this ic has a mos structure which is easily damaged by static electricity, so thorough measures should be taken to prevent electrostatic discharge. (12) always connect the v ss , gnd1 and gnd2/3 pins to the lowest potential applied to this ic; do not leave these pins open. the voltages applied to the power supply pins should be as follows. v ss = gnd1 = gnd2/3 v dd = v cc 1 v cc 2 = v cc 3.
42 CXA3503R sony code eiaj code jedec code package material lead treatment lead material package mass epoxy resin solder plating 42 alloy package structure 118 19 38 39 54 72 55 0.5 0.2 0.08 m 0.08 10.0 0.2 12.0 0.3 0.65 0.2 14.5 0.2 11.0 0.2 0.15 0.05 0.1 0.1 0 to 10 detail a a 0.1 72pin lqfp (plastic) lqfp-72p-l111 p-lqfp72-10x10-0.5 0.3g package outline unit: mm sony corporation

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